Effective Graph-Based Algorithm Design Using a Modified Carry-Save Adder

• Thulasi

  English

  Author

• Karthik Varma

  English

  Author

• Rithesh Kumar

  English

  Author

The complexity of many digital signal processing systems is eliminated by the introduction of
several well-structured algorithms and architectures for the construction of low complexity bit parallel
multiple constant multiplication (MCM) operations. The digit serial MCM purpose has not received much
consideration. By altering the carry save adder and applying it to the graph based (GB) algorithm, we discuss
in this work the challenge of improving the gate level delay in digit serial MCM architectures. Here, power
and latency may be greatly decreased, albeit at the expense of more space. Experimental results demonstrate
the ability of the suggested optimization algorithms and digit-serial MCM designs to develop finite impulse
response filters and digit-serial MCM operations. Compared to the current way, the suggested method
achieves greater speed by reducing the delay.

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